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基本穩壓限流電路設計
- 稽納二極體 & 特性
- 二極體穩壓電路
- 稽納二極體穩壓電路
- 串聯式穩壓電路
- 並聯式穩壓電路
基本 ZENER 穩壓電路
並聯式穩壓電路
串聯式穩壓電路
Cheap Voltage Regulator 5V to 3.3V
Basic Power Supply Current Limiting Circuit
Power Supply Circuit with feedback and Current Limiting
Power Supply with feedback and Transistor Current limiting
Current Limiter
Current Limiting using BJT
Variable (Adjustable) Current Limiter Circuit
This circuit provide automatic current limiting up to 8.4A. Unlike current limiter that uses only a resistor, this current limiting circuit doesn’t drop the voltage, or at least keep the voltage drop at minimum, until a certain current amount is exceeded. This current amount limit is adjustable from 1.4 A to 8.4A using a potentiometer. You can modify the component value to give different current limiting range. Here is the circuit’s schematic diagram:
The resistor R1 is there to sense the current. At R2 potentiometer at minimum resistance (the center tap connected to R1), if the current drawn by the load reach 1.2A then the voltage across R1 reach 0.6V and Q2 begin conducting, thus shorting the base voltage of Q4 to ground. This shorting action reduce the base current and therefore reduce the output voltage sensed by the load, and prevent the current to flow further. If you need the current limiter to limit at lower threshold range, you can change the R1 to 1R and you’ll get about 0.7A to 4.2A adjustment range.
Because of the power dissipation capability of 2N3055 transistor, at the worst case that the load is shorted to ground (zero resistance), if you limit the current to 8.4 A then the circuit can handle maximum source voltage of 14V, while limiting the current at 4.2A can handle up to 27V source voltage. The maximum voltage can be handled by this circuit is 60 volt, but at that maximum voltage you can only safely set the current limit at 1.9A in the extreme condition, when the load is shorted to ground. Please make sure the Q1 transistor has sufficient heat sink. [Circuit Schematic Source: Designed by FreeCircuitDiagram.Com
A current-limiting circuit both signals a latch-up condition and prevents latch-up- induced overcurrent destruction of a CMOS IC or group of ICs
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